# Generic coprocessor instructions

These are the generic coprocessor instructions implemented by all ARM processors with a coprocessor interface. Up to 16 coprocessors can be supported; all coprocessors have a number (CP#) in the range 0 to 15, and this must be specified in the instructions. Coprocessor 15 is used for cache, write-buffer and memory management control in several ARM processors, while coprocessors 1 and 2 are conventionally floating point units.

Coprocessors may have up to 16 directly addressable registers, C0-C15.

## Coprocessor data transfers

These instructions transfer data between a coprocessor and memory. The syntax is:

``

    op{condition}{L} CP#,Cd,[Rn {,#offset}]{!}
                [Rn],#offset

The memory address can be expressed in one of three ways, as shown above. In the first, pre-indexed form, an ARM register, Rn, holds the base address to which an offset can be added if necessary. Writeback of the effective address to Rn can be enabled using !. The offset must be divisible by 4, and within the range -1020 to 1020 bytes. With the second, post-indexed form, write-back of Rn+offset to Rn after the transfer, is automatic. Alternatively, a program-or-register-relative-expression can be used, in which case the assembler will generate a PC- or register-relative, pre-indexed address; if it is out of range an error will result.

L appended to the instruction specifies a long transfer; otherwise a short transfer takes place. The meaning of this is coprocessor-specific.

## Coprocessor data operations

This instruction is used for internal coprocessor operations. The syntax is:

``

    CDP{condition} CP#,CPOp,CRd,CRn,CRm{,CPOp2}

CPOp represents the coprocessor operation to be performed (four bits); details of such operations are coprocessor-specific and can be found in the appropriate datasheet. The operation is performed on CRn and CRm and the result written to CRd. The second, optional, CPOp2 field allows further variations on the operation (three bits).

## Coprocessor register transfers

The syntax of these two instructions is:

``

    op{condition} CP#,CPOp,Rd,Cn,Cm{,CPOp2}

CPOp is a 3-bit constant which specifies which variant of the instruction to perform. The selected operation is performed using the coprocessor registers Cn and Cm, and the result transferred to the ARM register Rd. If R15 is specified as the destination, only bits 28-31 of the result are transferred and are used to set the N, Z, C and V flags in the PSR without affecting the program counter. CPOp2, where present, is a 3-bit constant which sets the ARM condition flags, supporting the further coprocessor-specific sub-operations.

MRC is often used to read a coprocessor's status register(s), while MCR is used to write its control register(s). MRC, with R15 as the destination, supports execution of ARM code conditional on the result of an earlier coprocessor operation, (e.g. floating point compare).